Multiple mode frequency divider circuit

ABSTRACT

Providing various frequency and pulse repetition combinations, including single frequency, and two predetermined numbers of output pulses at each of two frequencies comprising a first cascade of flip-flops fed from a pulsing clock with means to tap two selected flip-flops in the cascade to set the two output frequencies. A second similar cascade of flip-flops includes means to set the two predetermined numbers of pulses. The two cascades are interconnected by means including control flipflops, whereby switching from one to the other settings on, and resetting of both arrays, are accomplished.

United States Patent [72] Inventor Donald F. Rhodes [56] References Cited Pmsbgrghy UNITED STATES PATENTS P 2 2,824,961 2/1958 Paivinen 32s/41x [22] Fled sem'261969 3 336 536 8/1967 Dame 307mm [45] Patented May 18,1971 [73] Assignee Gulf Research & Development Company Primary Examiner-Stanley T. Krawczewicz Pittsburgh, Pa. Att0rneysMeyer Neishloss, Deane E. Keith and William Kovensky ABSTRACT: Providing various frequency and pulse repetition combinations, including single frequency, and two predetermined numbers of output pulses at each of two [54] MODE FREQUENCY DWIDER frequencies comprising a first cascade of flip-flops fed from a 10 l D pulsing clock with means to tap two selected flip-flops in the aims rawmg cascade to set the two output frequencies. A second similar [52] US. Cl 328/41, cascade of flip-flops includes means to set the two predeter- 307/271 mined numbers of pulses. The two cascades are intercon- [511 int. Cl ..H03k 21/00 nected by means including control flip-flops, whereby [50] Field of Search 328/41, switching from one to the other settings on, and resetting of 140, 160; 307/271, 295 both arrays, are accomplished.

r20 /6 24 /a 7 :21 92 f T 94 26 7 a a /6\ Ah J. a4 86x '47 g; y 86 all 80 3 40? I .52 E r Patented May 18, 1971 NN W\ WVE/WOR. OO/VALD F. myopia-'5 MULTIPLE MODE FREQUENCY DIVTDER CIRCUIT This invention pertains to electronics, and particularly to a multiple mode, highly flexible frequency divider circuit.

More in detail, the circuit of the invention provides at least four different modes of operation. The simplest mode is a single frequency arrangement wherein the pulses supplied at a constant rate from the internal clock are put out at the output at the clocks or some other constant frequency. The second mode comprises first supplying, at the output, a predetermined number of pulses at a second predetermined frequency, and then reverting to the single frequency mode above. The third mode of operation comprises supplying a first predetermined number of pulses at a first frequency, and then a second predetermined number of pulses at a second frequency, and then repeating. The final mode of operation comprises first supplying a third predetermined number of pulses at said first frequency, and then reverting to. the third mode. The third predetermined number of pulses is the sum of the first and second predetermined numbers of pulses, and by suitable selection of the variable parameters within the circuit, said third predetennined number can be greater than the normal capacity of the pan of the invention which normally determines said first and second predetermined numbers of pulses.

The circuit of the invention has utility in the field of data handling generally, as will be apparent to those skilled in the art. More particularly, by way of example, the invention is useful in conjunction with multichannel, pulse height analyzers wherein it may be used to control a digital memory or data storage apparatus to provide different stepping times or recording times at each or each group of memory locations to accommodate different rates of production of the data to be recorded. An example of such a use is disclosed and claimed in copending patent application Ser. No. 861,383, filed Sept. 26, 1969, entitled Measuring Velocities in Multiphase Systems by John J. Day, Wilfred R. McLeod and Donald F. Rhodes, and assigned to the same assignee as the present invention.

As further general examples, the frequency divider circuit of the invention could be used in a computer, or other electronic equipment, wherein it is desirable to produce the effect of two or more clocks" from a single clock" mechanism built into the computer or other apparatus as well as retaining the single clock" or single frequency capability. Appropriate dials and switches may be provided on a control console to cut the circuit of the invention into and out of the larger timing circuits, and to dial or otherwise select the various time periods or frequencies and the various numbers of repetitions produced from the single built-in clock. As a corollary or further embodiment of this kind of application, the circuit of the invention can be used where it is desired to have a period of counting, or on time, and then a predetermined period of delay, by simply not utilizing one of the counts or time periods provided by the circuit of the invention in one of its at least dual modes of operation.

Another specific example of a use is in the field of analysis by radioactive irradiation wherein the circuit of the invention could be utilized to first control a period of time during which a neutron generator, an accelerator, or other device to irradiate a sample would be controlled by a first timing period, and then compatible detection means would be controlled by a second timing period. By suitable adjustment of the numbers of repetitions and the lengths of the time periods, as will be evident to those skilled in the art, method and apparatus can be devised to automatically so analyze a continuing series of samples.

ln those modes where there is first a single period and then some sort of cyclic operation, the first period could be used as a warmup" time, or a preparation time, or the like, in many schemes or systems for instrument control, process control, analysis, and the like. Other uses of the various modes of operation of the circuit of the invention will be apparent to those skilled in the art.

The above and other advantages of the invention will be pointed out or will become evident in the following detailed description and claims, and in the accompanying drawing also forming a part of the disclosure, in which the sole FlGURE is an electrical schematic diagram of a circuit embodying the invention.

Referring to the drawing, the circuit 10 comprises a clock 12 which provides pulses at a constant interval of time via a line 14. lf desired, a clock which provides a variable pulse interval could be used. THe essential elements of circuit 10 are a first array of flip-flops arranged in cascade numbered A0, A1, A2, etc., up to the last flip-flop Art. The circuit also includes a second array of cascaded flip-flops indicated by B0, B1, B2, etc., up to the last flip-flop Bn. These two cascaded arrays shall be designated the A chain and the B chain, respectively. As is readily apparent, the A chain can include any number of flip-flops to achieve any length of time interval, period, equal to the clock interval times two raised to a power equal to the number of the flip-flop, as will appear more clearly below. Similarly, the B chain can include any number of flip-flops to achieve any number of repetitions equal to two raised to a power equal to the number of a selected flip-flop. All the flip-flops in both the A and B chains, and the control flip-flops described below, are identical, and therefore only one flip-flop will be described in detail. A flip-flop is a solid state device in the nature of a double-throw switch, with the added capacities of remembering or holding a signal on either side, and of being reset to its initial condition. It is conventional in the art to refer to the two conditions in which the output of one side of a flip-flop could be as either the I state" or the 0 state, with the other side always being in the opposite condition. As used herein, the 1 state shall mean ground potential, and the 0 state a voltage of about 3 volts. This nomenclature has been added to the drawings and will facilitate the following description. Another characteristic of a flip-flop, depending on manufacturer, is that it will provide a signal on the output of a particular side only when that side goes from a higher level to a lower level, or vice versa. For example, referring to flip-flop A2, it will provide an output signal which will change the state of flip-flop A3 only when the right side of flip-flop A2 goes from the 0 state to the 1 state, that is, when the voltage goes from 3 volts to ground, a positive going pulse. The flip-flops used in the apparatus built to test the invention operate with positive going signals, but other apparatus could be build to work with negative going signals, as will be obvious to those skilled in this art. Flip-flops consume power and are connected to a power supply. The power supply portion of the circuit of the invention is not shown in full detail in that it is conventional as is understood by those skilled in the art. However, some parts of the power supply are shown, for convenience and reasons which will appear below, and these connections are indicated on the drawing by the notation of a V enclosed in a circle. It will further be understood in regard to the power supply that each of the connections are electrically isolated from the others by the use of suitable means, not shown, such as current limiting resistors, Zener diodes, and the like.

All of the A and B chain flip-flops are arranged in the circuit so that they are normally in the states shown, i.e., left side at 3 or 0 state, right side at ground or 1 state. Means are provided to reset the flip-flops to these initial conditions both during the course of operation and initially prior to starting operation. To this end, a line 16, having many branches, feeds the reset terminals on the A chain flip-flops and a similar line 18 serves to reset the B chain flip-flops. The two lines 16 and 18 terminate at a grounding switch 20 which includes a pair of manually operable, spring-loaded, normally open contacts 22 and 24 adapted to ground the lines 16 and 18, separately and respectively, which, via means in the flip-flops, sets them to the initial conditions shown. If the circuit is left idle for a period of time, the flip-flops could possibly wander into either state, which would cause a period of confused operation upon startup. The grounding switch 20 is operated prior to putting the circuit into use so that all the flip-flops will be in their initial states as shown Because of the particular nature of the flip-flops used, grounding at the initially O-state side will cause the flip-flop to take the configuration shown, i.e., that side at 3 volts or state.

Power is supplied to the A and B chain flip-flops by a pair of lines 26 and 28, respectively, and means not shown are provided to separately feed power to the other half of each flipfiop.

A composite connection 30 interconnects each two flipflops in the A'chain, and a similar composite connection 32 serves this same function in the B chain. Each connection 30 terminates in two contacts 34 and 36, and all the contacts 34 together comprise a set, any one of which may be contacted by a movable member 34a. Similarly, all the contacts 36 form a set selectively contactable by a moveable member 36a.

Physically, a single multiple gang switch or similar device may be provided to permit selective cooperation between any one contact 34 and their member 34a, and any one contact 36 and their cooperating movable member 360. Similar structure is provided for the B chain and comprises a set of contacts 38 cooperable with a member 38a and a second set of contacts 40 cooperable with a member 40a. if desired, only one set of contacts could be provided on the B chain, resulting in a simplification of the circuitry but at the cost of some of the flexibility. This modification is mentioned again in the Operation section below.

The regular pulses from clock l2 delivered by line 14 to flip-flop A0 will first cause that flip-flop to change states, and the next clock pulse will cause it to change back to its original state. As mentioned above, the second clock pulse thus causes flip-flop A0 to produce its first right side positive going output pulse, 0 state to 1 state, which causes flip-flop Al to change state for the first time via connection 30. Thus, each two pulses into any one flip-flop will cause one state change at the next higher flip-flop.

Thus, it can be seen that the clock pulses cascade up the A chain and are in effect counted therein. Any position of the moveable member will receive a pulse once every period of time proportional to the clock s frequency times two raised to a power equal to the number of the flip-flop at the output of which it is set. For example, contact 340, in the position shown, will conduct at a frequency having a period equal to the clock interval times 2. Similarly, contact 36a will conduct at a frequency having a period equal to the clock interval times 2', thus halving the clock frequency. Referring to the B chain, signals are delivered to flip-flop B0 via line 42 from control circuitry described below and the same logic with regard to the cascading and with regard to the contacts 38a and 40a, as described above with regard to the contacts 340 and 36a, applies. The B chain will be referred to again in the Operation portion below.

Control means are provided to interconnect the A and B chains and comprises an output line 44 branching off of the B chain feeder line 42. Line 44 includes an amplifier, a one-shot multivibrator, or other suitable device 46, the conditioned pulses from which are utilized in other circuitry, such as the analytical apparatus described in the copending application referred to above, or by any other point of use.

The interconnecting or control means also comprises a pair of AND gates 48 and 50, the outputs of which feed line 42, and a line 52 interconnecting lines 42 and 16. A line 54 interconnects moveable member 340 and comprises the second input to AND gate 48. A line 56, in a similar manner, interconnects member 36a and AND gate 50. The two lines 54 and 56 are shown as having an indeterminate length so as to enable the respective moveable member to contact any one of all of the contacts of its cooperating set.

As is known, an AND gate is a solid state device which will produce a signal at its output when there are signals on all, in this case both, of its input lines. An AND gate also inverts signals from its input across to its output. A pair of lines 58 and 60 comprises the second input to each of the two AND gates 48 and 50, respectively, and the other ends of said lines are connected to each of the two sides of a control flip fiop 62.

Control flip-flop 62 is provided with a pair of switches 64 and 66 which serve to ground either side of said flip-flop so that its initial state can be manually controlled. The nature of switches 64 and 66 is such that they may be either momentarily operated, or closed until manually opened, for a reason which will appear below.

The remainder of the control circuitry comprises another pair of AND gates 68 and 70, a second control flip-flop 72 and a third pair of AND gates 74 and 76. A grounding switch 78 is included in the power supply to the 0 state or left side of flipflop 72 for reasons which willappear below. I

A line 80 conducts the signal from moveable member 38a to AND gates 76 and 68, and to the input of the initial 0 state side of flip-flop 72. A line 82 conducts the signal from moveable member 40a to AND gates 70 and 74 and to the input of the initial l-state side of the flip-flop 72. A line 84 conducts the output signal of the l-state side of the flip-flop 72 to AND gates 76 and 68. A line 86 conducts the signal from the output of the O-state side of flip-flop 72 to AND gates 74 and 70.

The output of AND gate 70 comprises the input to the initial l-state side of flip-flop 62 via a line 88, and a line 90 connects the output of AND gate 68 to the input of the initial 0- state side of flip-flop 62. A pair of lines 92 and 94 conduct output signals from AND gates 74 and 76 to reset line 18.

OPERATION As will appear in more detail below, the two control flipfiops 62 and 72 enable one moveable member on each chain, depending on the state or configuration of the control flipflop. That is, in the configuration shown, members 36a and 40a are enabled to effect the circuit because the various AND gates they feed already have one of the necessary two inputs, lines 60 and 86 have a signal on them. Similarly, members 340 and 38a are disabled to effect the circuit because the AND gates they feed do not yet have even one of the necessary two inputs, no signals on lines 58 and 84.

in all modes of operation of the circuit of the invention, clock 12 provides a pulse once every some time interval, that is, at the frequency built into the clock, for example, once every 10,000th of a second. Mathematically, frequency and period are reciprocals, and both terms are somewhat interchangeably in this specification. For ease of reference below, let the clock interval be called x. THe examples described below were not taken from test results in order thaT relatively small numbers could be used in this explanation. The principles of operation, however, are the same. In all modes, switches 22 and 24 are first operated momentarily to bring all the A and B chain flip-flops to their initial conditions as shown. Switches 66 and 78 are also operated momentarily for this same purpose, unless otherwise indicated for the particular mode of operation.

Since all four of the moveable members 34a, 36a, 38a and 40a can be made to cooperate with any one contact of their respective sets of contacts, all references in the following examples to long counts or short counts or to particular numbers, or to particular frequencies or repetitions, are purely exemplative. Four differently numbered flip-flops, namely A2, A5, B4, and B7 were purposely chosen to avoid confusion, but all of these are interchangeable. In summary, any moveable member can cooperate with any flip-flop, independently of the other moveable member on that cascaded array.

in all of the following modes an output signal on either one of AND gates 48 or 50 does three things: (1) each such signal is an output signal delivered to device 46 via lines 42 and 44; (2) each such signal is fed to the beginning of the B chain to operate the B chain in the same manner that clock pulses operate'the A chain; and (3) each such signal resets the A chain via lines 42, 52, and 16.

As shown in the drawing and as described herein, four different modes of operation are contemplated, but there may be additional modes of operation in the apparatus as shown, or with only minor changes thereto. The four modes are as follows:

Mode One. This is the simplest mode and comprises simply a single frequency, the entire B chain and associated controls being bypassed. To achieve this result, the operator need only close switch 66 associated with control flip-flop 62 and leave it closed. Upon so doing, flip-flop 62 will go to the state shown and will stay there. Upon initiation of clock pulses a single will be present at member 36a once every two clock pulses, in the configuration shown in the drawing. Since the bottom half, in the drawing, of flip-flop 62 is in the 0 state, a single of -3 volts will be present on line 60 comprising one of the inputs to AND gate 50. Upon the occurrence of two clock pulses, a signal of 3 volts will be present on member or contact 36a and line 56, thus causing AND gate 50 to conduct and putting out a signal on line 42. The signal on line 42 will comprise the first output signal on line 44 and to device 46, and will also reset the A chain via lines 52 and 16. These pulses on line 42 will cascade up the B chain, but this will have no effect on output line 44 since flip-flop 62 is locked to the state shown.

It is to be noted that the flip-flops require a positively going, 0 to 1, pulse to change states, but that the various AND gates require two negative signals to produce a positive, actually ground potential, output signal. As mentioned above, an AND gate is also an inverter. Thus, the clock frequency can be picked up directly. if member 36a were set on the lowest contact 36, between flip-flops A0 and Al, the very first clock pulse would cause the right side of A0 to go from 1 to 0 thus producing a 3 volt signal input to AND gate 50 and an output pulse on line 42. Thus, it can be appreciated that the numbering of the flip flops is significant, i.e., setting member 3611 for the flip-flop A0 output produces the clock frequency as follows; 2X=X, where X is the period of the clock frequency, since two raised to the zero power equals one. Similarly, setting member 360 as shown cuts the output frequency to half the clock frequency; the period equals 2 X or 2X, since two raised to the one power equals two. Thus, the single frequency produced in the first mode, and one or both of the frequencies or repetitions in the other modes, can be the clock frequency, or one repetition. Generally, any period, or number of repetitions, determined by raising two to a power equal to the number of the flip-flops can be obtained. Of course, the same logic applies to the numbering of the B chain flip-flop.

Mode Two. In this mode, it is desired to first have a predetermined number of pulses at a predetermined frequency, and then to revert to the single frequency mode one above. For example, eight pulses at a period of 2X, then endless pulses at a period of 16X. In order to accomplish this end, the operator simply closes switch 78 so that it stays closed. As described above, an output pulse on line 42 will be produced once every two clock pulses, the initial l-state side of flip-flop 62 conducting at this time causing a 3 volt signal to be present on line 58. When eight such pulses have been produced, flip-flop B3 will change state producing a 3 volt signal at its contact 40, which signal then proceeds via moveable member 40a and line 82 to AND gate 70. There is a signal on line 36 feeding AND gate 70 causing line 88 to conduct, which causes the upper side of flip-flop 62 to flip from its initial 1 state to its 0 state, producing a 3 volt signal which is fed to AND gate 48 via line 58. Thereafter, no occurrence on the B chain can have any effect on the A chain since flip-flop 72 is locked into the configuration shown in the drawing by closure of switch 78. Since 72 is locked in this mode, line 84 can never carry a signal, gate 68 will never conduct, and flip-flop 62 will never change back to the configuration shown in the drawing after having flipped once. The single frequency thereafter produced will have a period equal to 2 X, which is determined by the setting of contact 34a.

Mode Three. In this mode of operation it is desired to supply, on output line 44, a first predetermined number of pulses at a first frequency, then asecond predetermined number of pulses at a second frequency, and so on. For example, first eight pulses at a period of 2X, then 2 pulses at a period of 16X. This mode of operation is achieved by leaving all three switches 64,66, and 78 in their normally open condition, after having momentarily operated 66 and 78 to achieve initial conditions. The clock pulses delivered to the A chain will produce output pulses on line 44 once every time interval or period equal to 2X and will do so eight times (2). Upon the B3 flipflop changing state, the sequence of events is that AND gate 70 fires causing flip-flop 62 to change state and the B chain to reset via AND gate 74 firing, a signal being present on line 86 feeding both AND gates 70 and 74. The B chain resetting is accomplished on lines 92 and 18. Upon the B chain being reset, a positive going pulse is produced at moveable member 40a causing flip-flop 72 to change states. The positive going pulse which causes flip-flop 72 to change state is produced because the left side of flip-flop B3 has been changed from its initial 0 state, arrival at which was the end of the count of eight pulses, back to the I state by the resetting signal on line 18. Thus, the interaction of the B chain and flip-flop 72 is inherently properly timed because the B chain arriving at the set count first causes 62 to change state and causes one of AND gates 74 or 76 to reset the B chain. The resetting of the B chain then causes 72 to change state. Thus, the next clock pulse enters the system with both chains reset and both flipflops 62 and 72 in configuration opposite that shown. AND gates 48,68, and 76 each have one input, and the circuit will now produce 2 output pulses on line 44 at a period of 2 X, after which the circuit will go back into the configuration shown, and so forth in a cyclic manner.

Mode Four. In this mode of operation it is desired to supply on output line 44 a third predetermined number of pulses at a first frequency, and to then revert to mode three operation as above. For example, first 2-l-2 pulses at a period of 2 X; then into mode three with 2 pulses at a period of 2 X, and then 2 pulses at a period of 2X; and continuing the mode three cycle. This mode of operation is achieved by momentarily closing switch 64 so that flip fiop 62 only is initially in a configuration opposite that shown. Clock pulses will cascade up the A chain to flip-flop A4 and will cause AND gate 48 to fire, no signal being present on line 60 to AND gate 50. After eight repetitions, flip-flop B3 will have changed state, a signal will be present on line 82 from moveable member 40a, and AND gate 70 will fire, a signal being present on line 86. This signal on line 88 from AND gate 70 will not cause flip-flop 62 to change state. Flip-flop 72 however will change state since AND gate 74 will also fire providing a signal on line 18 resetting the B chain, thus causing flip-flop 72 to change state as described above. As arranged in the circuit herein, only a positively going signal can cause a flip-flop to change state from 1 to 0 states. The signal created on line 88, therefore, cannot cause flip-flop 62 to change state since the upper half, in the drawing, of said flip-flop already has an output of -3 volts (0 state). After the B chain has reset, and flip-flop 72 has changed state, clock pulses continue to cascade up the A chain to the posi tion of contact 34a which again causes AND gate 48 to fire. After 2 0 repetitions, a signal will be present on line 80. The signal on line will cause AND gates 68 and 76 to fire, caus ing flip-flop 62 to change state, causing resetting of the B chain to cause a change of state of flip-flop 72. Thereafter, mode three operation is achieved, as explained above. Thus, in this mode four operation, it is possible to create a number of repetitions, even larger than the normal capacity of the B Chain, prior to reverting back to mode three operation. For example, if the two moveable members 38a and 40a were both set at the output of En, the first period would have a number of repetitions equal to double the normal B chain capacity.

As an incidental matter, closing switch 64 and leaving it closed would be equivalent to closing switch 66, mode one single frequency operation, except that. the single frequency would be determined by member 34a rather than 36a. This is not a different mode.

As mentioned above, it is to be understood that all moveable members are shown in exemplitive positions, and any member can be put atany position on its respective chain. ln this regard, the two members on either chain could be placed at the output of the same flip-flop. if this were done on the A chain, only one frequency would be produced, effectually bypassing the B chain. if it were done on the B chain, only one repetition rate would result, but for two different frequencies if desired, thus producing the same effect as would one set of contacts and one moveable member only on the B chain. Apparatus with only one set of contacts and one moveable member on the B chain has been built and used, flip-flop '72 and the associated parts of the control means having been omitted.

in apparatus which has been built in successfully testing, the invention, all of the flip-flops, AND gates, and clock l2 were obtained from Digital Equipment Corporation, their 100, 200 and 400 lines of solid state components. The other components, such as the various switches, multivibrator 46, and power supply not shown, are standard items, as is well known to those skilled in the art.

As is known, the response times of the various flip-flops and other solid state components is virtually instantaneous, on the order of IO seconds, which is considered negligible with respect to the frequency of pulse production at clock 12, which at the fastest is of the orders of magnitude of 10' seconds. Thus it can be seen that the two frequencies at which output pulses are produced are a function of solely the number of flip-flops activated times X, the clock interval, and not the response times of the components utilized.

While the invention has been described in detail above, it is to be understood that this detailed description is by way of example only, and the protection granted is to be limited only within the spirit of the invention and the scope of the following claims.

lclaim:

l. A method of frequency division utilizing an electronic circuit, which circuit includes a constant frequency pulse source, comprising the steps of l. feeding the pulses from the pulse source to an input end of a first array of flip-flops arranged in cascade;

2. individually selectively tapping said first array at first and second locations thereon, A. selecting said first and second locations to determine two output pulse frequencies;

3. feeding signals from a selected one of said first and second locations to A. an output line,

B. the input end of a second array of flip-flops arranged in cascade, and

C. to means to reset said first array;

4. individually selectively tapping said second array at at least one location thereon,

A. selecting said at least one location to determine at least one output pulse repetition rate;

5 feeding signals from said at least one location on said second array to control means to A. deactivate said selected one of said first and second locations on said first array and to activate the other of said first and second locations on said first array, and

B. reset said second array.

2. The method of claim 1, tapping said second array at a second location thereon, selecting said second location to determine a second output pulse repetition rate, and wherein said step of feeding signals from said at least one location comprises feeding signals from a selected one of said first and second locations to said control means to additionally deactivate said selected one of said first and second locations on said second array and to activate the other of said first and second locations on said second array.

3. The method of claim 1, and bringing all the flip-flops to a known initial condition prior to said step of feeding pulses from the pulse source to said input end of said first array.

4. A frequency divider circuit comprising clock means adapted to produce pulses at a constant predetermined rate, first and second arrays of flip-flops each arranged in cascade,

means to feed the clock means pulses to the input end of said first cascaded array, first and second sets of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said first cascaded array, at least one set of contacts connected in parallel circuit to each of the outputs of each of the flip flops of said second cascaded array, a moveable member associated with each of said sets of contacts and adapted to cooperate with any one contact only of its associated set, an output line, control means interconnecting all of said moveable members, said output line, and the input end of said second cascaded array, said control means comprising means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said first cascaded array, said control means comprising means to feed signals from said selected moveable member to said output line and to the input end of said second cascaded array, said control means comprising means to feed signals from the moveable member associated with said at least one set of contacts on said second cascaded array to said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to switch from one to the other as to the selected one of the pair of moveable members enabled thereby.

5. The circuit of claim 4, a second set of contacts respectively connected in parallel circuit to the contacts of said at least one set of contacts on said second cascaded array and a moveable member associated therewith, said control means comprising second means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said second cascaded array, and said control means comprising means to feed signals from said selected moveable member associated with said second cascaded array to both of said means to selectively enable a moveable member to cause both said means to selectively enable a moveable member to from one to the other, as to the selected one of the pair of moveable members enabled thereby.

6. The circuit of claim 5, said first and second means to selectively enable a moveable member comprising first and second control flip-flops respectively.

7. The circuit of claim 6, grounding switch means associated with said first control flip-flop to prevent said first control flipflop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.

8. The circuit of claim 6, grounding switch means associated with said first control flip-flop to pemiit said first control flipflop to make one switch only from one to the other and thereafter to prevent said first control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.

9. The circuit of claim 6, grounding switch means associated with said second control fliP-flop to prevent said second control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.

10. The circuit of claim 4, and grounding switch means for each of said first and second cascaded arrays, whereby all of said flipflops may be brought to a known initial condition by operation of said grounding switch means prior to feeding the first clock means pulse to the input end of said first cascaded array. 

1. A method of frequency division utilizing an electronic circuit, which circuit includes a constant frequency pulse source, comprising the steps of
 1. feeding the pulses from the pulse source to an input end of a first array of flip-flops arranged in cascade;
 2. individually selectively tapping said first array at first and second locations thereon, A. selecting said first and second locations to determine two output pulse frequencies;
 3. feeding signals from a selected one of said first and second locations to A. an output line, B. the input end of a second array of flip-flops arranged in cascade, and C. to means to reset said first array;
 4. individually selectively tapping said second array at at least one location thereon, A. selecting said at least one location to determine at least one output pulse repetition rate;
 5. feeding signals from said at least one location on said second array to control means to A. deactivate said selected one of said first and second locations on said first array and to activate the other of said first and second locations on said first array, and B. reset said second array.
 2. individually selectively tapping said first array at first and second locations thereon, A. selecting said first and second locations to determine two output pulse frequencies;
 2. The method of claim 1, tapping said second array at a second location thereon, selecting said second location to determine a second output pulse repetition rate, and wherein said step of feeding signals from said at least one location comprises feeding signals from a selected one of said first and second locations to said control means to additionally deactivate said selected one of said first and second locations on said second array and to activate the other of said first and second locations on said second array.
 3. The method of claim 1, and bringing all the flip-flops to a known initial condition prior to said step of feeding pulses from the pulse source to said input end of said first array.
 3. feeding signals from a selected one of said first and second locations to A. an output line, B. the input end of a second array of flip-flops arranged in cascade, and C. to means to reset said first array;
 4. individually selectively tapping said second array at at least one location thereon, A. selecting said at least one location to determine at least one output pulse repetition rate;
 4. A frequency divider circuit comprising clock means adapted to produce pulses at a constant predetermined rate, first and second arrays of flip-flops each arranged in cascade, means to feed the clock means pulses to the input end of said first cascaded array, first and second sets of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said first cascaded array, at least one set of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said second cascaded array, a moveable member associated with each of said sets of contacts and adapted to cooperate with any one contact only of its associated set, an output line, control means interconnecting all of said moveable members, said output line, and the input end of said second cascaded array, said control means comprising means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said first cascaded array, said control means comprising means to feed signals from said selected moveable member to said output line and to the input end of said second cascaded array, said control means comprising means to feed signals from the moveable member associated with said at least one set of contacts on said second cascaded array to said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to switch from one to the other as to the selected one of the pair of moveable members enabled thereby.
 5. feeding signals from said at least one location on said second array to control means to A. deactivate said selected one of said first and second locations on said first array and to activate the other of said first and second locations on said first array, and B. reset said second array.
 5. The circuit of claim 4, a second set of contacts respectively connected in parallel circuit to the contacts of said at least one set of contacts on said second cascaded array and a moveable member associated therewith, said control means comprising second means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said second cascaded array, and said control means comprising means to feed signals from said selected moveable member associated with said second cascaded array to both of said means to selectively enable a moveable member to cause both said means to selectively enable a moveable member to from one to the other, as to the selected one of the pair of moveable members enabled thereby.
 6. The circuit of claim 5, said first and second means to selectively enable a moveable member comprising first and second control flip-flops respectively.
 7. The circuit of claim 6, grounding switch means associated with said first control flip-flop to prevent said first control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.
 8. The circuit of claim 6, grounding switch means associated with said first control flip-flop to permit said first control flip-flop to make one switch only from one to the other and thereafter to prevent said first control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.
 9. The circuit of claim 6, grounding switch means associated with said second control fliP-flop to prevent said second control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.
 10. The circuit of claim 4, and grounding switch means for each of said first and second cascaded arrays, whereby all of said flip-flops may be brought to a known initial condition by operation of said grounding switch means prior to feeding the first clock means pulse to the input end of said first cascaded array. 